Symposium A

Paper Title
EUVL R&D at NewSUBARU Synchrotron Light Facility
Short Biography
Takeo Watanabe is now Full Professor, Director of Center for EUVL (CEL) at Laboratory of Advanced Science and Technology for Industry (LASTI), and Special Assistant to the President, University of Hyogo. He is expert of the EUV lithographic technologies for electronic devices and works in the EUVL field more than 30 years.
He started his work for R&D of 64MBit DRAM technologies at the Central research lab. of Sharp Corporation in Japan, 1990. After that he joined the Himeji Institute of Technology (present University of Hyogo, Japan) in 1996. LASTI operates the NewSUBARU synchrotron light facility which is the largest synchrotron facility operated by university in Japan. EUVL related research is carried out at NewSUBARU, and many contributions related to the technology of resist, mask, optics etc. have being done on EUV lithography at NewSUBARU.
He has authored over 250 technical papers and received many awards.
He is the President of the International Conference of Photopolymer Science and Technology (ICPST). He is also Chair of organizing committee of the International Conference of Photomask Japan.
He is committee member of IEEE International Roadmap of Devices and Systems.

Paper Title
Functional surface treatment primer (FSTP) toward High NA EUV lithography
Short Biography
Wataru Shibayama graduated Tokyo university of agriculture and technology as master degree.
Then he joined Nissan Chemical corporation as the chemical researcher for advanced lithography process in 2007.
His current main work focuses the development of new organic & inorganic photoresist-related materials for next generation lithography process.

Paper Title
Recent development of photoresist modeling in preparation of high-NA EUV Lithography
Short Biography
Alex is a physicist and engineer with more than 15 years of experience in lithography. After his master in ST-Microelectronics in double patterning techniques, and his first PhD in Numonyx/Micron in Immersion lithography, he joined IMEC for a second PhD in EUVL in 2009. Through a deep dive into roughness and stochastic phenomena, he learns all aspect of the litho-process: source, mask, optical system, and photoresists. In 2012 he joined KLA in the R&D group for computational lithography: PROLITH. With more than 50 publications and several patents, he now oversees customers relationship and support, applications, and software improvement.

Paper Title
Low Stochastics for Extreme UV Patterning: Photoresists with precise molecular weight, composition and sequence
Short Biography
Christopher Kemper Ober is the Francis Bard Professor of Materials Engineering at Cornell University. His research is focused on lithography, patterning, the biology materials interface, and control of surface structure in thin films. Ober is a member of the National Academy of Engineering. Ober was honored in 2015 with the Photopolymer Science & Technology Outstanding Contribution Award. In 2014 he was a JSPS Fellow in Japan. He was elected a fellow of the American Physical Society (2014) and the American Association for the Advancement of Science (2015) and is a SPIE Senior Member (2018).

Paper Title
Dry resist metrology readiness for high-NA EUVL
Short Biography
Gian F. Lorusso received his PhD in solid state physics from the University of Bari, Italy, in 1992. He has been working on topics related to the semiconductor industry such as metrology tool development, lithography, material analysis and more. His domains of expertise include lithography, metrology, microscopy, and spectrometry. After working at the École Polytechnique Fédérale de Lausanne (Switzerland), the Center for X-ray Lithography (Wisconsin), the Center for X-ray Optics at Lawrence Berkeley National Laboratories (California), and KLA-Tencor (California), he has joined IMEC (Belgium) in 2006. His work has produced more than 230 papers and 17 patents, and was awarded with both the Vladimir Ukraintsev and Diana Nyyssonen awards. He is working on Extreme Ultraviolet Lithography and Metrology, fields in which he started in the early nineties.

Paper Title
Wafer-scale characterization for 2D material layers
Short Biography
Alain Moussa received his bachelor’s degree in chemistry from la haute Ecole Leonard de Vinci of Bruxelles, Belgium, in 2000.
He has worked at Catholic University of Louvain-La-Neuve in research for polymer synthesis and thin film deposition on silicon as well as their characterization by XRR, AFM, ellipsometry and SEM.
Since 2005, he has joined IMEC, where he is working in Scanning Probe Microscopy domain, and today, in metrology department for lithography patterning and process control, as R&D engineer.

Paper Title
High repeatability and low shrinkage solution using CD-SEM for EUV resist
Short Biography
Masaki Sugie received his master's degree in 2015 from the Department of Informatics at Kogakuin University after working on super-resolution technology for commercial displays. He joined Hitachi High-Tech Corporation in 2015. He was initially engaged in the image processing development of semiconductor inspection equipment and has been working on application development since 2021. He has been assigned to imec as a Hitachi assignee since July 2023.

Paper Title
Relationship between shot noise (stochasticity) and diffusion (smoothing) in resist processes for extreme ultraviolet lithography
Short Biography
Takahiro Kozawa is a professor of SANKEN, Osaka University. He earned his BS and MS degrees in nuclear engineering from the University of Tokyo, and Ph. D. degree in chemical engineering from Osaka University in 1990, 1992, and 2003, respectively. His work is mainly focused on beam-material interaction and beam-induced reactions in resist materials.

Paper Title
Fueling the Scaling Roadmap with Vertical Integration: a Patterning Perspective
Short Biography
Luciana received her B.S. in Chemical Engineering from the National University of Mexico, and her PhD from University of Texas at Austin in 2007, where her worked focused on self-assembly of polymer nanocomposites. After post-doctoral work at University of Minnesota and Rensselaer Polytechnic Institute, Luciana started her career at IBM Microelectronics at Fishkill in 2013, working in enabling attainment of defect control targets in 22SOI and 14SOI technologies. In 2014 she moved to Albany where she has been focusing on defectivity characterization and yield improvement of EUV patterning processes and materials. Through this work, she enabled new track processes, film controls, and EUV mask defectivity methodologies critical for IBM’s EUV lithography leadership and partner manufacturing adoption, and has been instrumental in generating the infrastructure necessary to understand stochastic defectivity in EUV lithography. She is now the senior manager for Patterning and Metrology in IBM Semiconductors at Albany Nanotech.

Paper Title
High NA EUV insertion into DRAM: Opportunities and challenges
Short BiographyDr. Ryoung-han Kim focuses on technology strategy, patterning, OPC, mask, design, and design-technology co-optimization (DTCO). He currently serves as the director responsible for design, OPC, and mask tapeout at IMEC, overseeing various R&D initiatives across semiconductor logic, memory, and patterning programs.
Dr. Kim is also a member of the semiconductor community, serving as the associate editor at the JM3 journal and committee member for the SPIE advanced lithography and patterning program. He previously served as the program chair for the SPIE advanced lithography and patterning program from 2021 to 2023, and involved in the committee of the IEEE Design Automation Conference (DAC).
He worked as a Senior Manager of patterning R&D at GLOBALFOUNDRIES, which was spun off from Advanced Micro Devices (AMD), where he initiated his industrial career and gained valuable pioneering experience in patterning R&D activities. He also served as a Senior Member of the technical staff in Texas Instrument's fabless division.
Dr. Kim holds a Ph.D. degree in Electrical Engineering from Texas A&M University, College Station, Texas, USA, and B.S. and M.S. degrees from Yonsei University, Seoul, Korea.

Paper Title
High NA EUV progress towards introduction in high-volume semiconductor manufacturing
Short Biography
Jara G. Santaclara is High NA EUV Product Manager at ASML. She has broad experience in EUV lithography, scanner performance and processing. Jara is internationally recognized for collaborations carried out with resist and materials suppliers within the EUV ecosystem, and for the work presented in several related conference papers.

Paper Title
Impact of HighNA half-field to full-field overlay performance by MonteCarlo simulations
Short Biography
Romain Lallement is a Senior Research Engineer at IBM's Semiconductor Research in Albany, NY, leading a patterning team. With expertise in photolithography, mask processes, and device technology, he aligns IBM's roadmap with process development to achieve device performance goals.
After earning a Master's degree in Material Science from Polytech Marseille, France, in 2005, Romain worked at STMicroelectronics as a photolithography engineer. There, he qualified CMOS and eNVM technologies to rigorous standards for automotive, bio-medical, and security applications.
In 2016, Romain joined IBM Research, delivering cutting edge patterning solutions for FinFET and Gate All Around (GAA) technology. He became IBM Albany's mask technology lead, innovating Extreme Ultraviolet (EUV) mask processes for 28nm pitch single-exposure yields.
Romain has co-authored articles and holds 7 US and international patents.

Paper Title
Direct print EUV patterning of tight pitch metal layers for Intel 18A process technology node
Short Biography
Dr. Raguraman Venkatesan is a Principal Engineer in Intel's Logic Technology Development at Portland Oregon, USA. He received a BTech degree from Indian Institute of Technology, Bombay and PhD degree from Georgia Institute of Technology, Atlanta, both in Electrical Engineering. He has worked in Intel for over 20 years, where he has invented several Optical proximity correction techniques for lithographic patterning of all process technology nodes from 90nm through 18Angstroms. His current research interests include next generation EUV lithography and advanced patterning technologies. He loves travelling the world with his wife and two kids.

Paper Title
Multi-beam mask writer MBM-3000 for next generation EUV mask production
Short Biography
Dr. Issei Aibara received his Ph.D. in Optical Engineering from Tokushima University, Japan and joined NuFlare Technology Inc. in 2020. He is currently working on development of multi-beam mask writers.

Paper Title
Mask innovations on the eve of High NA EUV lithography
Short Biography
Vicky Philipsen received her PhD degree in solid-state physics from the University of Leuven (Belgium) in 2001. At imec she joined the Advanced Patterning department, where her research domain involves the imaging and masks aspects in lithography (from 193nm to EUV, high NA and hyper NA EUV) both by simulations and experiments.
She is leading the project on novel EUV masks at imec.
She is team leader of the imaging and reticles team in the imec Advanced Patterning department.
She has authored or co-authored ~150 papers published in international conference proceedings and technical journals. She is member of the SPIE ALP conference committee.

Paper Title
Ultra-High productivity Etch Process for Beyond 10μm Depth Memory Channel Hole of 3DNAND Flash Devices
Beyond 10 µm Depth Ultra-High Speed Etch Process with 84% Lower Carbon Footprint for Memory Channel Hole of 3D NAND Flash over 400 Layers
Short Biography
Maju Tomura, as an Expert, focuses on development of plasma etching process with high aspect ratio (HAR) structure for memory applications, for example, 3D-NAND and DRAM at Advanced Process Development Laboratory in Tokyo Electron Miyagi Limited. He received the master degree in the nano-mechanics engineering from Tohoku University in 2011. He joined in Tokyo Electron Miyagi Ltd. in the same year. he had been engaging in wide variety of plasma etching process, such as high aspect hole etch for memory applications and quasi- Atomic Layer Etching (Quasi-ALE) for Self- alignment structure in logic device.