MNC 2025 Fireside Chat

Short Biography
Singh is VP Advanced Technology at NVIDIA, working to improve the computations involved in the design and manufacture of semiconductors, using accelerated computing and AI. He was previously an Intel Fellow and Director of their Computational Imaging Department, leading the development of industry-first solutions in diffractive optics, microscopic inspection, and chip design. Vivek is an SPIE Fellow. He served as president of the Lithography Workshop, honorary visiting professor at Jawaharlal Nehru University in New Delhi, and founding member and chair of the Design Technology Co-Optimization conference in SPIE. Vivek has a B.Tech. from IIT Delhi and a Ph.D. from Stanford.

Short Biography
Harry J. Levinson is currently a lithography consultant. He is the author of three books: Lithography Process Control, Principles of Lithography, and Extreme Ultraviolet Lithography. Levinson is an SPIE Fellow, previously chaired the SPIE Publications Committee, and served on SPIE’s Board of Directors. He received the Society’s 2014 Directors’ Award. In 2022 he received the SPIE Frits Zernike Award in Microlithography. Levinson is currently Editor-in-Chief of the Journal of Micro/Nanopatterning, Materials and Metrology (JM3). His Ph.D. thesis addressed certain phenomena involving the interactions of light and matter. For this work, he received the Wayne B. Nottingham Prize in surface science.

Short Biography
Dr. Jiyoung Kim is a Professor in Materials Science and Engineering at the University of Texas at Dallas, with over 30 years of expertise in semiconductor process, device and characterization particularly related to atomic layer deposition (ALD), including advanced EUV resist development using ALD/VPI processes. Dr. Kim has served several conference and symposium chairs, including 2013 ALD conference. He has about 400 peer-reviewed journal and proceeding papers, and his works have been cited more than 13,000 times

Short Biography
Seiji Nagahara is the Head of Technical Marketing at ASML Japan. Prior to joining ASML, he served as Senior Director at Tokyo Electron Ltd. (TEL) for the development and marketing of advanced coater/developer systems. He began his career as a lithography engineer at NEC, later working at NEC Electronics and Renesas Electronics.
Dr. Nagahara has collaborated with leading institutions such as Toshiba, IMEC, UC Berkeley, and Argonne National Laboratory, contributing to global lithography research.
He holds B.E., M.E., and Ph.D. degrees in engineering from Osaka University. Dr. Nagahara has authored numerous papers, book chapters, and patents, and is a frequent speaker at international conferences. He is a SPIE Fellow and serves in various committee roles, including Vice President of SPST, Program Chair of ICPST, and former Chair of both the Program Committee and Steering Committee for MNC. He is also actively involved in IRDS, SEMICON Japan, SPIE, and other industry organizations.