MNC 2016, November 8-11, 2016
29th International Microprocesses and Nanotechnology Conference
ANA Crowne Plaza Kyoto, Kyoto, Japan

''Design Technology CoOptimization, the key to unlocking new scaling pathways''
Lars Liebmann, Fellow, GLOBALFOUNDRIES, USA
Design Technology CoOptimization (DTCO), born out of the necessity for closer collaboration between designers and lithographers at increasingly restrictive sub-resolution technology nodes, has become a vital component for efficient scaling in advanced technology nodes. The downside of using increasingly complex resolution enhancement techniques and multiple exposure patterning solutions to maintain the industry's aggressive pace of scaling without mayor advances in exposure tool resolution is that design rules become very restrictive and design flows become very complicated. In effect, there is a rapidly increasing 'scaling handicap' that reduces the achievable chip area scaling as a function of feature pitch scaling. Compensating for this 'scaling handicap' by over-scaling the feature pitches quickly becomes counter productive in terms of cost-per-function scaling since the technology cost and complexity rapidly increase as minimum feature pitch decreases. To achieve the desired cost-per-function scaling DTCO has to take a holistic view of the scaling challenge and explore all pathways to increasing transistor density while minimizing escalation in process cost and complexity. For digital standard-cell design flows the achievable scaling can be simplified to:
(Poly Pitch x Cell Width) x (Metal Pitch x Cell Height) / Placement Utilization
- Cell Width, measured in number of poly tracks, describes the width of each logic function.
- Cell Height, measured in number of wiring tracks, describes the minimum height of a viable cell image for the most aggressively scaled cell size.
- Placement Utilization measures how densely the cells can be placed before routing becomes overly congested. 
For many generations technology scaling has focused primarily on reducing pitches, often at the cost of degrading the other scaling parameters.
This paper will illustrate how a holistic DTCO approach can be employed to co-optimize technology features, design-rule-arcs, cell architectures, and place-and-route solutions to maximize technology scaling at a given set of resolution challenged pitches.
Short Biography
Lars Liebmann, now a Fellow with GLOBALFOUNDRIES, received BS and MS degrees in Nuclear Engineering and a PhD in Engineering Physics from Rensselaer Polytechnic Institute, Troy, NY. He joined IBM in 1991 where he began his work on resolution enhancement techniques such as alternating phase shift, optical proximity correction, and off-axis illumination with sub-resolution assist features. As these resolution enhancement techniques became increasingly complex and layout invasive. Dr. Liebmann found himself interacting with the design community earlier and more fundamentally in every technology node. These engagements on restrictive design rules, lithography friendly design, and multiple exposure patterning enhanced design flows laid the foundation for what is now known as design-technology co-optimization. After the transition to GLOBALFOUNDRIES, Dr. Liebmann continues to focus on design-technology co-optimization as a means of developing robust technology definitions in the early stages of leading-edge technology nodes. He holds over 60 patents, has published over 40 technical papers, has received IBM’s Corporate and Outstanding Technical Achievement awards, is a fellow of SPIE,  and earlier this year published his first book: ‘Design Technology Co-Optimization in the Era of Sub-resolution IC Scaling'

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