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Abstract
Design Technology CoOptimization (DTCO), born out of the necessity for
closer collaboration between designers and lithographers at increasingly
restrictive sub-resolution technology nodes, has become a vital component
for efficient scaling in advanced technology nodes. The downside of using
increasingly complex resolution enhancement techniques and multiple exposure
patterning solutions to maintain the industry's aggressive pace of scaling
without mayor advances in exposure tool resolution is that design rules
become very restrictive and design flows become very complicated. In effect,
there is a rapidly increasing 'scaling handicap' that reduces the achievable
chip area scaling as a function of feature pitch scaling. Compensating
for this 'scaling handicap' by over-scaling the feature pitches quickly
becomes counter productive in terms of cost-per-function scaling since
the technology cost and complexity rapidly increase as minimum feature
pitch decreases. To achieve the desired cost-per-function scaling DTCO
has to take a holistic view of the scaling challenge and explore all pathways
to increasing transistor density while minimizing escalation in process
cost and complexity. For digital standard-cell design flows the achievable
scaling can be simplified to:
(Poly Pitch x Cell Width) x (Metal Pitch x Cell Height) / Placement
Utilization
Where:
- Cell Width, measured in number of poly tracks, describes the width of
each logic function.
- Cell Height, measured in number of wiring tracks, describes the minimum
height of a viable cell image for the most aggressively scaled cell size.
- Placement Utilization measures how densely the cells can be placed before
routing becomes overly congested.
For many generations technology scaling has focused primarily on reducing
pitches, often at the cost of degrading the other scaling parameters.
This paper will illustrate how a holistic DTCO approach can be employed
to co-optimize technology features, design-rule-arcs, cell architectures,
and place-and-route solutions to maximize technology scaling at a given
set of resolution challenged pitches.
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