\n
![\"\"](\"https:\/\/imnc.jp\/2024\/wp-content\/uploads\/2024\/04\/Kagawa_sama.jpg\")
\nPAPER TITLE <\/Strong>
\nNovel 3D Stacking Process Technologies to Evolve CMOS Image Sensors<\/td>\n<\/tr>\n
SHORT BIOGRAPHY <\/Strong> SHORT BIOGRAPHY <\/Strong> SHORT BIOGRAPHY <\/Strong>
\nYoshihisa Kagawa is a general manager of Research Division at Sony Semiconductor Solutions Corporation. He joined Sony Corporation in 2004 and he has been a specialist for BEOL and 3D-stacking process integration. Especially, he contributed to launch Sony\u2019s Cu-Cu hybrid bonding process and announced its rollout at IEDM 2016. Currently, he manages the research and development of process integration for stacked CMOS image sensors. He is a committee member of IEEE Electronic Components and Technology Conference (ECTC) and IEEE International Interconnect Technology Conference (IITC).
\n SHORT ABSTRACT<\/Strong>
\nIn the field of CMOS Image Sensors (CIS), there has been high demand for new functions that can respond various photo taking scenes. We have developed the stacked Back Illuminated-CIS (BI-CIS), composed of conventional BI-CIS technology and standard logic technology. To realize the fine-pitch and large-scale electrical connection between upper CIS chip and lower logic chip, we have developed the wafer-to-wafer Cu-Cu hybrid bonding technology and successfully introduced it to our stacked BI-CIS in 2015. Since then, to fabricate more advanced stacked BI-CISs we have developed various kinds of novel process technologies: 3-wafers stacking process, chip-to-wafer stacking process and ultra-fine pitch Cu-Cu hybrid bonding. In this talk, the process technologies that have evolved the stacked BI-CIS will be discussed.<\/td>\n<\/tr>\n\n\t
\n![\"\"](\"https:\/\/imnc.jp\/2024\/wp-content\/uploads\/2024\/07\/Dr.Schoot.jpg\")
\nPAPER TITLE <\/Strong>
\nThe next step in Moore\u2019s Law: High NA EUV is here<\/td>\n<\/tr>\n\n\t
\nAt this moment EUV systems equipped with a 0.33 Numerical Aperture (NA) have proven themselves and are successfully applied in high volume manufacturing. The next step is 0.55 NA and is ready to enter mass production.
\nThis so-called high NA scanner, targeting an ultimate resolution of 8nm, will bring multiple benefits to the semiconductor market such as reduction of process complexity, yield improvement, higher resolution enabling printability of smaller features at increased density, and cost of technology reduction. It will extend Moore\u2019s law for at least another decade.
\nA novel lens design, capable of providing the required Numerical Aperture, has been identified; this so called anamorphic lens will provide 8nm resolution in all orientations. Paired with new, faster stages and more accurate sensors providing the tight focus and overlay control needed it enables future nodes.
\nIn this talk, I will sketch an overview of the path of more than 12 years development of the High NA EUV scanner. This resulted into a full functional tool, of which the current imaging and overlay performance will be shown. The results are taken from the first tool that resides in the High NA lab.
\nJan B.P. van Schoot, PhD, Fellow and Senior Function System Engineer, ASML, Netherlands.
\nAfter his study Electrical Engineering (Cum Laude) at Twente University of Technology, he received his PhD in Physics on the subject of non-linear optical waveguide devices and held a post-doc position studying waveguide based electro-optical modulators.
\nHe joined ASML in 1996 and was Project Leader for the Application of the first scanner and its successors up to 5500\/750. In 2001 he became Product Development Manager of Imaging Products (DoseMapper, Customized Illumination). In 2007 he joined System Engineering. He was responsible for the Optical Columns of the 0.25NA and 0.33NA EUV systems. After this he worked on the design of the EUV source. He was the study leader of the High-NA EUV system and is now responsible for the High-NA optical train and investigating future extensions.
\nHe is an ASML-Fellow and Fellow of the International Society of Optics and Photonics (SPIE), holds over 55 independent patents and presents frequently at conferences about photo lithography.
\n<\/td>\n<\/tr>\n\n\t
\n![\"\"](\"https:\/\/imnc.jp\/2024\/wp-content\/uploads\/2024\/10\/Saito_sama.jpg\")
\n
\nJapan\u2019s Semiconductor Strategy<\/td>\n<\/tr>\n\n\t
\nHisashi Saito is deputy director of IT Industry Division at Ministry of Economy, Trade and Industry (METI). He joined METI in 2021 and he worked on semiconductor R&D budgets and Japan\u2019s semiconductor strategies. Prior to joining METI, he was involved in R&D of GaN and Si power semiconductors and GaN high-frequency semiconductors at a Japanese semiconductor company.
\n SHORT ABSTRACT<\/Strong>
\nThree years have already passed since the Ministry of Economy, Trade and Industry formulated the \u201cSemiconductor and Digital Industry Strategy\u201d for 2021, and the global situation has changed dramatically. Responding to economic security risks, making the semiconductor supply chain more resilient, and addressing digitalization and greening have become more realistic issues. For this reason, we have just revised our strategy in June last year. This presentation will provide an overview of specific strategies and initiatives, including last year's revision and subsequent updates, mainly related to semiconductors.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/h3>\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_uag_custom_page_level_css":"","footnotes":""},"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false,"page_builder_slider_small":false,"size1":false,"size2":false,"size3":false,"size4":false,"size5":false,"size6":false,"size7":false,"size8":false,"size9":false,"size10":false,"size11":false,"size12":false,"size-card":false},"uagb_author_info":{"display_name":"mnc2022","author_link":"https:\/\/imnc.jp\/2024\/author\/mnc2022\/"},"uagb_comment_info":0,"uagb_excerpt":null,"_links":{"self":[{"href":"https:\/\/imnc.jp\/2024\/wp-json\/wp\/v2\/pages\/251"}],"collection":[{"href":"https:\/\/imnc.jp\/2024\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/imnc.jp\/2024\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/imnc.jp\/2024\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/imnc.jp\/2024\/wp-json\/wp\/v2\/comments?post=251"}],"version-history":[{"count":8,"href":"https:\/\/imnc.jp\/2024\/wp-json\/wp\/v2\/pages\/251\/revisions"}],"predecessor-version":[{"id":1676,"href":"https:\/\/imnc.jp\/2024\/wp-json\/wp\/v2\/pages\/251\/revisions\/1676"}],"wp:attachment":[{"href":"https:\/\/imnc.jp\/2024\/wp-json\/wp\/v2\/media?parent=251"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}